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Low-, medium- and high-density reset and clock control (RCC)
RM0008
1.
2.
if the APB prescaler is 1, the timer clock frequencies are set to the same frequency as
that of the APB domain to which the timers are connected.
otherwise, they are set to twice (×2) the frequency of the APB domain to which the
timers are connected.
FCLK acts as Cortex?-M3 free running clock. For more details refer to the ARM Cortex?-
M3 Technical Reference Manual.
6.2.1
HSE clock
The high speed external clock signal (HSE) can be generated from two possible clock
sources:
●
●
HSE external crystal/ceramic resonator
HSE user external clock
The resonator and the load capacitors have to be placed as close as possible to the
oscillator pins in order to minimize output distortion and startup stabilization time. The
loading capacitance values must be adjusted according to the selected oscillator.
Figure 9.
HSE/ LSE clock sources
Clock source
Hardware configuration
OSC_OUT
External clock
(HiZ)
External
source
OSC_IN OSC_OUT
Crystal/Ceramic
resonators
C L1
Load
C L2
capacitors
External source (HSE bypass)
In this mode, an external clock source must be provided. It can have a frequency of up to 25
MHz. You select this mode by setting the HSEBYP and HSEON bits in the Clock control
register (RCC_CR) . The external clock signal (square, sinus or triangle) with ~50% duty
cycle has to drive the OSC_IN pin while the OSC_OUT pin should be left hi-Z. See Figure 9 .
78/995
Doc ID 13902 Rev 9
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